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87354ami www.icst.com/products/hiperclocks.html rev. a june 27, 2003 1

ics87354i 4/5 d ifferential - to -2.5v/3.3v lvpecl c lock g enerator preliminary g eneral d escription the ics87354i is a high performance 4/5 dif- ferential-to-2.5v/3.3v ecl/lvpecl clock genera- tor and a member of the hiperclocks? family of high performance clock solutions from ics. the clk, nclk pair can accept most standard differ- ential input levels. the ics87354i is characterized to operate from either a 2.5v or a 3.3v power supply. guaranteed output and part-to-part skew characteristics make the ics87354i ideal for those clock distribution applications demanding well defined performance and repeatability. f eatures 1 differential 2.5v/3.3v lvpecl / ecl output 1 clk, nclk input pair clk, nclk pair can accept the following differential input levels: lvpecl, lvds, lvhstl, sstl, hcsl maximum output frequency: 250mhz input frequency: >1ghz translates any single ended input signal to 3.3v lvpecl levels with resistor bias on nclk input output skew: 38ps (maximum) part-to-part skew: 375ps (maximum) propagation delay: 2.1ns (maximum) lvpecl mode operating voltage supply range: v cc = 2.375v to 3.8v, v ee = 0v ecl mode operating voltage supply range: v cc = 0v, v ee = -2.375v to -3.8v -40c to 85c ambient operating temperature b lock d iagram p in a ssignment ics87354i 8-lead soic 3.90mm x 4.90mm x 1.37mm package body m package top view clk nclk mr f_sel 1 2 3 4 hiperclocks? ,&6 vcc q nq v ee 8 7 6 5 q nq clk nclk 4 mr 5 r 0 1 f_sel the preliminary information presented herein represents a product in prototyping or pre-production. the noted characteristics a re based on initial product characterization. integrated circuit systems, incorporated (ics) reserves the right to change any circuitry or specific ations without notice.
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ics87354i 4/ 5 d ifferential - to -2.5v/3.3v lvpecl c lock g enerator preliminary t able 1. p in d escriptions t able 2. p in c haracteristics r e b m u ne m a ne p y tn o i t p i r c s e d 1k l ct u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 2k l c nt u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i 3r mt u p n in w o d l l u p , h g i h n e h w . d e l b a n e e r a s t u p t u o , w o l n e h w . t e s e r r e t s a m . h g i h t u p t u o q n d n a w o l t u p t u o q g n i c r o f t e s e r s i r e d i v i d . s l e v e l e c a f r e t n i l t t v l / s o m c v l 4l e s _ ft u p n in w o d l l u p . 3 e l b a t n i d e b i r c s e d s a s t u p t u o q n , q r o f e u l a v r e d i v i d s t c e l e s . s l e v e l e c a f r e t n i l t t v l / s o m c v l 5v e e r e w o p. n i p y l p p u s e v i t a g e n 7 , 6q n , qt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 8v c c r e w o p. n i p y l p p u s e v i t i s o p : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k ? r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k ? t able 3. f unction t able r ml e s _ fe u l a v e d i v i d 1x h g i h t u p t u o q n , w o l t u p t u o q : t e s e r 00 4 01 5 f igure 1. t iming d iagram clk mr q
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ics87354i 4/ 5 d ifferential - to -2.5v/3.3v lvpecl c lock g enerator preliminary t able 4a. p ower s upply dc c haracteristics , v cc = 2.375v to 3.8v, v ee = 0, t a = -40 c to 85 c t able 4c. d ifferential dc c haracteristics , v cc = 2.375v to 3.8v, v ee = 0, t a = -40 c to 85 c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e v i t i s o p 5 7 3 . 23 . 38 . 3v i e e t n e r r u c y l p p u s r e w o p d b ta m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i k l cv c c v = n i v 8 . 3 =0 5 1a k l c nv c c v = n i v 8 . 3 =5a i l i t n e r r u c w o l t u p n i k l cv c c v , v 8 . 3 = n i v 0 =5 -a k l c nv c c v , v 8 . 3 = n i v 0 =0 5 1 -a v p p e g a t l o v t u p n i k a e p - o t - k a e p 5 1 . 03 . 1v v r m c ; e g a t l o v t u p n i e d o m n o m m o c 2 , 1 e t o n v e e 5 . 0 +v c c 5 8 . 0 -v v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 1 e t o n h i . v s i k l c n , k l c r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e e l g n i s r o f : 2 e t o n c c . v 3 . 0 + l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i 2v c c 3 . 0 +v v l i e g a t l o v w o l t u p n i 3 . 0 -8 . 0v i h i t n e r r u c h g i h t u p n il e s _ f , r mv c c v = n i v 8 . 3 =0 5 1a i l i t n e r r u c w o l t u p n il e s _ f , r mv c c v , v 8 . 3 = n i v 0 =5 -a t able 4b. lvcmos/lvttl dc c haracteristics , v cc = 2.375v to 3.8v, v ee = 0, t a = -40 c to 85 c a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5 v outputs, i o continuous current 50ma surge current 100ma package thermal impedance, ja 112.7 c/w (0 lfpm) storage temperature, t stg -65 c to 150 c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability.
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ics87354i 4/ 5 d ifferential - to -2.5v/3.3v lvpecl c lock g enerator preliminary t able 5. ac c haracteristics , v cc = 2.375v to 3.8v, v ee = 0, t a = -40 c to 85 c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p n i 1 >z h g t d p ; y a l e d n o i t a g a p o r p 1 e t o n ) f i d ( q o t k l c5 6 . 11 . 2s n t ) o ( k s4 , 2 e t o n ; w e k s t u p t u o 8 3s p t ) p p ( k s4 , 3 e t o n ; w e k s t r a p - o t - t r a p 5 7 3s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 0 20 0 6s p . t n i o p g n i s s o r c t u p t u o l a i t n e r e f f i d e h t o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e m : 1 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n s e g a t l o v y l p p u s e m a s e h t t a g n i t a r e p o s e c i v e d t n e r e f f i d n o s t u p t u o n e e w t e b w e k s s a d e n i f e d : 3 e t o n d e r u s a e m e r a s t u p t u o e h t , e c i v e d h c a e n o s t u p n i f o e p y t e m a s e h t g n i s u . s n o i t i d n o c d a o l l a u q e h t i w d n a . s t n i o p s s o r c l a i t n e r e f f i d e h t t a . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 4 e t o n t able 4d. lvpecl dc c haracteristics , v cc = 2.375v to 3.8v, v ee = 0, t a = -40 c to 85 c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u ov c c 4 . 1 -v c c 0 . 1 -v v l o 1 e t o n ; e g a t l o v w o l t u p t u ov c c 0 . 2 -v c c 7 . 1 -v v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p 5 6 . 09 . 0v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n ? v o t c c . v 2 -
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ics87354i 4/ 5 d ifferential - to -2.5v/3.3v lvpecl c lock g enerator preliminary p arameter m easurement i nformation o utput r ise /f all t ime d ifferential i nput l evel 3.3v o utput l oad ac t est c ircuit scope qx nqx lvpecl v cc = 2v t pd p ropagation d elay v ee = -1.8v -0.375v clock outputs 20% 80% 80% 20% t r t f v sw i n g v cmr cross points v pp v cc v ee clk nclk clk nclk q nq t sk(pp) nqx qx nqy qy part 1 part 2 p art - to -p art s kew o utput s kew t sk(o) nqx qx nqy qy
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ics87354i 4/ 5 d ifferential - to -2.5v/3.3v lvpecl c lock g enerator preliminary a pplication i nformation figure 1 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v cc /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio f igure 1. s ingle e nded s ignal d riving d ifferential i nput he clock layout topology shown below is a typical termina- tion for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that gen- erate ecl/lvpecl compatible outputs. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 3.3v f out f in 5 2 z o z o 5 2 z o 3 2 z o 3 2 z o = 50 ? z o = 50 ? rtt = 1 (v oh + v ol / v cc ? 2) ? 2 z o z o = 50 ? z o = 50 ? 50 ? 50 ? rtt v cc - 2v f in f out ? 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 2a and 2b show two different layouts which are recommended only as guidelines. other suitable clock lay- outs may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. t ermination for lvpecl o utputs f igure 2b. lvpecl o utput t ermination f igure 2a. lvpecl o utput t ermination w iring the d ifferential i nput to a ccept s ingle e nded l evels of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v cc = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. v_ref r1 1k c1 0.1u r2 1k single ended clock input clk nclk vcc
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ics87354i 4/ 5 d ifferential - to -2.5v/3.3v lvpecl c lock g enerator preliminary f igure 3c. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvpecl d river f igure 3b. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvpecl d river f igure 3d. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvds d river 3.3v r1 50 r3 50 zo = 50 ohm lvpecl zo = 50 ohm hiperclocks clk nclk 3.3v input r2 50 zo = 50 ohm input hiperclocks clk nclk 3.3v r3 125 r2 84 zo = 50 ohm 3.3v r4 125 lvpecl r1 84 3.3v d ifferential c lock i nput i nterface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 3a to 3e show inter- face examples for the hiperclocks clk/nclk input driven by the most common driver types. the input interfaces suggested f igure 3a. h i p er c lock s clk/ n clk i nput d riven by ics h i p er c lock s lvhstl d river here are examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example in figure 3a, the input termination applies for ics hiperclocks lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. 1.8v r2 50 input lvhstl driver ics hiperclocks r1 50 lvhstl 3.3v zo = 50 ohm zo = 50 ohm hiperclocks clk nclk f igure 3e. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvpecl d river with ac c ouple zo = 50 ohm r3 125 hiperclocks clk nclk 3.3v r5 100 - 200 3.3v r2 84 3.3v r6 100 - 200 input r5,r6 locate near the driver pin. zo = 50 ohm r1 84 r4 125 c2 lvpecl c1 zo = 50 ohm r1 100 3.3v lvds_driv er zo = 50 ohm receiv er clk nclk 3.3v
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ics87354i 4/ 5 d ifferential - to -2.5v/3.3v lvpecl c lock g enerator preliminary r eliability i nformation t ransistor c ount the transistor count for ics87354i is: tbd t able 6. ja vs . a ir f low t able ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 153.3 c/w 128.5 c/w 115.5 c/w multi-layer pcb, jedec standard test boards 112.7 c/w 103.3 c/w 97.1 c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
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ics87354i 4/ 5 d ifferential - to -2.5v/3.3v lvpecl c lock g enerator preliminary p ackage o utline - m s uffix t able 7. p ackage d imensions reference document: jedec publication 95, ms-012 l o b m y s s r e t e m i l l i m n u m i n i mm u m i x a m n8 a5 3 . 15 7 . 1 1 a0 1 . 05 2 . 0 b3 3 . 01 5 . 0 c9 1 . 05 2 . 0 d0 8 . 40 0 . 5 e0 8 . 30 0 . 4 ec i s a b 7 2 . 1 h0 8 . 50 2 . 6 h5 2 . 00 5 . 0 l0 4 . 07 2 . 1 0 8
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ics87354i 4/ 5 d ifferential - to -2.5v/3.3v lvpecl c lock g enerator preliminary t able 8. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patent s, or licenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability, or other ext raordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without noti ce. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pt n u o ce r u t a r e p m e t i m a 4 5 3 7 8 s c ii a 4 5 3 7 8c i o s d a e l 8e b u t r e p 6 9c 5 8 o t c 0 4 - t i m a 4 5 3 7 8 s c ii a 4 5 3 7 8l e e r d n a e p a t n o c i o s d a e l 80 0 5 2c 5 8 o t c 0 4 -

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